Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate training and inference for large-scale AI models. Today’s AI performance is frequently limited by system-level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, software, and systems to unlock greater GPU utilization, reduce capital and power costs, and maximize data center efficiency. The company’s solutions and value proposition have been validated by several leading hyperscalers.

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED company and developer of the first augmented reality contact lens).

We are seeking a highly skilled and visionary Performance Modeling Engineer to drive the definition, development, and application of Eridu AI’s architectural and performance modeling infrastructure. In this role, you will set the direction for modeling efforts that directly influence our ASIC architecture and microarchitecture (uArch) designs. You will collaborate closely with system architects, chip designers, and cross-functional teams to evaluate design trade-offs, identify bottlenecks, and deliver actionable insights that shape the future of large-scale AI networking. This is an opportunity to establish a modeling strategy at the cutting edge of AI hardware while working alongside a team of talented performance engineers.

• Participate in the development and deployment of high-level performance models for networking devices to guide architectural decisions.
• Define modeling methodologies and frameworks that ensure consistency, accuracy, and scalability across projects.
• Partner closely with ASIC architects and uArch teams to evaluate trade-offs in throughput, latency, power, and area.
• Drive performance analysis and bottleneck identification to inform and influence architecture and design choices.
• Oversee the creation and validation of structural and traffic models to explore real-world workloads and system scenarios.
• Establish and champion best practices for performance modeling, documentation, and reporting.
• Communicate modeling results, insights, and recommendations to senior technical and leadership stakeholders.

• MSEE/PhD in Electrical Engineering, Computer Engineering, or a related field with 10+ years of relevant industry experience.
• Proven track record of technical leadership in performance modeling or architecture for ASICs, SoCs, or networking systems.
• Deep expertise in networking protocols such as Ethernet and PCIe.
• Proficiency in modeling languages and tools, including C, C++, Python, and scripting environments.
• Strong background in FPGA/ASIC design flows, including synthesis, simulation, and verification tools (e.g., Verilog, VHDL, Synopsys, Cadence).
• Demonstrated ability to drive architectural discussions and influence design trade-offs through modeling insights.
• Excellent analytical and problem-solving abilities with a data-driven approach.
• Strong communication skills with the ability to present complex technical information clearly and persuasively.

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.