ASIC Physical Design Engineer, Principal in SAINT PAUL, Minnesota at ForwardEdge ASIC LLC

At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design.

As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents.

We are looking for highly experienced ASIC Physical Design / Static Time Analysis (PD/STA) Engineer to work onsite in our St. Paul, MN office to support ASICs, IPs and Chiplet designs. This role is targeted at senior level candidates who can operate with a high degree of RTL2GDS PD implementation and sign-off for tape out.

• Lead and collaborate with Analog, Verification, Logic and Physical design team members on all design implementation aspects from Synthesis to Tape-Out of various IPs, test chips and SoC/ASIC designs.

• Lead with hands-on experience with synthesis, block and chip level implementation with industry standard PnR, STA and EMIR flows and tools

• Lead end-to-end timing closure at block/chip levels including MCMM flows and ECO flows

• Collaborate with cross functional teams to problem solve solutions across new and changing tools, flows and methodologies

• Mentor junior and senior PD engineers through technical reviews, methodology guidance, and hands-on support.

• Improve productivity through automation, infrastructure, and methodology enhancements.

• Support project planning by identifying risks, tracking progress, and communicating status to technical and program leadership.

Qualifications

• BS in Electrical, Electronics, Computer Engineering, or 15 years of experience in related field or MS in Electrical, Electronics, Computer Engineering, or 12 years of experience in related field or Ph.D. with 8 years of experience in related field

• Experience in advanced technology nodes and understanding of deep sub-micron design problems/solutions and ability to drive design closure in a fast-paced environment

• Strong experience in SOC/ASIC design flows, tools and methodologies.

• Knowledge of low power design flows such as power gating, multi-Vt, Voltage scaling techniques

• Excellent understanding of logic design fundamentals and gate/transistor level implementation

• Strong programming skills in Tcl/Perl/Shell/Python

• Effective communicator with the ability to influence cross-functional teams.

• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off

• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO

• Incentives: Eligibility for short-term and long-term incentive programs