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What is the role of a 2027 Summer Intern - Logic Design at ForwardEdge ASIC LLC?

The 2027 Summer Intern - Logic Design position at ForwardEdge ASIC LLC is a Full-Time opportunity in the relevant field.

Where is this 2027 Summer Intern - Logic Design job located?

SAINT PAUL, Minnesota, 55108, United States

What industry does this 2027 Summer Intern - Logic Design position belong to?

This role spans multiple industries.

2027 Summer Intern - Logic Design job near me in SAINT PAUL, Minnesota at ForwardEdge ASIC LLC | Jobs and Employment

Position Description:

At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design.

As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents.

We are currently accepting applications for 2027 Summer Internships within our Logic Design Engineering team.

Position Summary

As a Logic Design Engineer Intern, you will be developing ASIC and FPGA designs that will be included in an array of complex, innovative and exciting products. Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will benefit from the experience of highly qualified digital design engineers on the team. You will work closely with verification, analog design, physical design, and architecture teams.

Responsibilities include, but are not limited to the following:

• Working under the direction of experienced engineers/architects to understand the function and requirements for entry-level design blocks.

• Writing detailed implementation plans and specifications for design blocks.

• Writing Register Transfer Level (RTL) code using industry standard hardware description languages.

• Writing lower-level test bench code to verify baseline functionality and features for design blocks.

• Writing test plans and coordinating with the Design Verification team to fully verify design blocks.

• Synthesizing RTL code using industry standard tools and analyzing results.

• Providing RTL updates to meet Power, Performance and Area (PPA) or Size, Weight and Power (SwaP) requirements.

• Writing and executing plans for the post silicon lab validation.

Qualifications:

• Actively working toward a bachelor’s or master’s degree in electrical engineering or computer engineering.

• Strong course work in VLSI design, digital logic

• Proficiency or intermediate level Programming skills such as Python

• Strong analytical and problem-solving skills with attention to detail

• Excellent communication and teamwork skills; ability to work in a fast-paced engineering environment

• US citizenship

Join ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world.

2027 Summer Intern - Logic Design in SAINT PAUL, Minnesota at ForwardEdge ASIC LLC

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