IO Architect in San Jose, California at TylSemi, Inc.

About TylSemi, Inc.

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.

• No endless meetings, no PowerPoint presentations to convince middle management.

• US team: Bay Area preferred, but we hire the best people regardless of location

• India team: Building a world-class design center in Bangalore

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.

• Bias for action. We move fast. Analysis paralysis doesn't fly here.

• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

• Low ego, high standards. We don't care about titles or politics. We care about results.

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

The Role

As the HSIO Architect, you will own the high-speed interface architecture across the various product families. You will drive decisions from SerDes architecture to UCIe die-to-die integration, working directly with the Head of Engineering, digital leads, and analog teams. You will also serve as the technical interface to key IP vendors (UCIe PHY, SerDes), foundry partners and anchor customers.

This is not an IP integration role. We need someone who can define the architecture, validate the tradeoffs, and guide execution through tape-out.

Key Responsibilities

Architecture & Definition

• Define high-speed IO architecture for PCIe/Ethernet-224G/448G scale-up fabric/CPO-optics to electrical interfaces

• Define die-to-die interface architecture for UCIe integration: flit formats, credit-based flow control, sideband management, and latency targets

• Architect the SerDes-to-photonics interface, retimer integration, and co-packaged optics (CPO) readiness

• Own the signal integrity budget: TX/RX equalization, channel loss allocation, crosstalk margins, and jitter decomposition across the full channel

Implementation Oversight

• Guide SerDes PHY selection and evaluation; assess vendor IP (custom vs. licensed), and establish integration requirements

• Define and review UCIe PHY integration: bump map, power domain partitioning, analog/digital co-design requirements, and pad ring architecture

• Collaborate with digital architecture lead on protocol bridge design — PCIe TLP ↔ UCIe flit conversion, flow control, error handling

• Drive DFT and compliance test architecture for PCIe certification and UCIe conformance testing

• Establish PVT margin strategies and power management per-lane DVFS, shutdown sequences, and IVR chiplet coordination

Customer & Ecosystem Engagement

• Serve as primary technical interface to anchor customers and engaging hyperscaler architecture teams (AWS, Google, Microsoft, Meta) to validate product definition against platform requirements

Roadmap & IP

• Contribute to RTL reuse strategy — enabling derivative roadmap SKUs with minimal re-spin

• Identify and scope patentable innovations in UCIe integration, adaptive equalization, and multi-protocol bridge architectures

Required Qualifications

• 15+ years in high-speed interface architecture; 5+ years at Principal level or higher in a fabless or IDM semiconductor environment

• Deep expertise in PCIe architecture — from PHY layer through controller and protocol stack; direct tape-out experience strongly preferred

• UCIe standard familiarity — flit-based transport, sideband protocol, and die-to-die integration in 2.5D/3D packages

• Signal integrity expertise: S-parameter analysis, channel simulation (HSPICE/IBIS-AMI), eye diagram closure, and crosstalk budgeting

• Experience with advanced nodes and advanced packaging (CoWoS, EMIB, InFO)

• Track record of driving complex multi-party IP integrations from architecture through tape-out

Preferred Qualifications

• Experience with 224G/400G+ SerDes architectures for scale-up AI fabric (NVLink, UALink, Ultra Ethernet, or proprietary)

• Familiarity with electrical-optical co-design for CPO or near-package optics; EIC retimer or photonic interface experience

• Prior work in chiplet-based multi-die architectures — bumping strategy, KGD handling, heterogeneous integration

• PCIe-SIG membership or active contribution to UCIe Consortium working groups

• Prior startup experience or comfort with early-stage ambiguity and fast-paced execution