Senior Engineer – Static Timing Analysis (STA) in Bangalore, Karnātaka at TylSemi, Inc.

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.

• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location

• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.

• Bias for action. We move fast. Analysis paralysis doesn't fly here.

• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are seeking a highly skilled Senior Engineer – Static Timing Analysis (STA) to join the Physical Design team. In this role, you will be responsible for driving timing closure and signoff activities for complex SoC designs across advanced technology nodes. You will collaborate with synthesis, place-and-route, CTS, and ECO teams to ensure robust timing convergence and successful tapeout delivery. The ideal candidate should possess strong STA fundamentals, signoff expertise, and hands-on experience with industry-standard timing tools.

What You’ll Do

Perform block-level and full-chip Static Timing Analysis for setup, hold, recovery, removal, and noise checks Drive timing closure by debugging and resolving timing violations across multiple modes and corners Develop and validate timing constraints including SDC generation and timing exception management Work closely with synthesis, CTS, P&R, and ECO teams to optimize timing, area, and power Execute MMMC timing analysis using industry-standard STA methodologies Perform ECO implementation and timing signoff for advanced-node designs Support tapeout activities and ensure clean timing signoff delivery

What We’re Looking For

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline 5+ years of experience in STA, timing closure, or Physical Design signoff roles Strong understanding of STA concepts including setup/hold analysis, clock skew, jitter, and timing exceptions Hands-on experience with Synopsys PrimeTime and timing signoff methodologies Good understanding of synthesis, CTS, place-and-route, and ECO flows Proficiency in Tcl, Perl, Python, or Shell scripting for automation and flow enhancement

Good to Have

Experience with advanced nodes such as 7nm, 5nm, or below Exposure to low-power methodologies including UPF/CPF and power-aware STA Knowledge of SI/noise analysis, OCV/AOCV/POCV methodologies, and timing convergence techniques

Success in This Role Looks Like

Achieving timing closure with clean setup and hold signoff across all modes and corners Efficiently resolving complex timing violations with minimal impact on area and power Improving STA productivity through automation and methodology enhancements Successful support of tapeout milestones with high-quality timing signoff

Location

Hybrid / On-site – Bengaluru / Remote - India