Principal Physical Design Engineer in Bangalore, Karnātaka at TylSemi, Inc.

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.

• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location

• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.

• Bias for action. We move fast. Analysis paralysis doesn't fly here.

• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are seeking a highly experienced Principal Physical Design Engineer to lead complex ASIC/SOC physical implementation activities across advanced technology nodes. The role requires deep expertise in full-chip and block-level implementation, technical leadership in achieving best-in-class PPA (Power, Performance, Area), and ownership of high-quality tape-outs. The ideal candidate will collaborate closely with cross-functional teams and drive methodology improvements, design closure strategies, and mentoring initiatives. 1

What You’ll Do

Lead end-to-end physical design implementation from floorplanning through GDSII signoff for complex SOCs and subsystems. Define and drive implementation strategies for timing, congestion, power, area, IR/EM, and signal integrity closure. Collaborate with RTL, STA, DFT, Packaging, and CAD teams to resolve complex design and integration challenges. Own physical signoff including timing, DRC, LVS, IR drop, EM, and reliability analysis. Drive advanced node implementation methodologies and optimize design QoR across multiple projects. Develop and improve automation scripts, flows, and reusable methodologies for implementation efficiency. Lead technical reviews, mentor junior engineers, and provide project execution guidance. Support tape-out activities and customer/escalation debugging when required.

What We’re Looking For

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. 12+ years of hands-on experience in ASIC/SOC physical design implementation. Strong expertise in floorplanning, placement, CTS, routing, timing closure, and physical verification. Hands-on experience with EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, StarRC, and Voltus/RedHawk. Deep understanding of advanced node challenges including low-power design, SI, IR/EM, and variability analysis. Proven experience delivering successful tape-outs at advanced technology nodes (7nm/5nm/3nm preferred). Strong scripting and automation skills using Tcl, Python, Perl, or Shell. Excellent problem-solving, leadership, communication, and stakeholder management skills.

Good to Have

Experience with hierarchical SOC integration and top-level implementation. Exposure to 3D IC, chiplet, or package-aware implementation methodologies. Experience in AI/ML-driven EDA optimization techniques.

Success in This Role Looks Like

Successful delivery of complex SOC designs meeting aggressive PPA and schedule targets. Consistent achievement of implementation and signoff closure with high-quality tape-outs. Improved team productivity through methodology enhancements and automation. Strong technical leadership, mentoring impact, and cross-functional collaboration.