Design Verification Engineer in Remote, Karnātaka at TylSemi, Inc.

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.

• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location

• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.

• Bias for action. We move fast. Analysis paralysis doesn't fly here.

• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

TylSemi Solutions Private Limited is looking for a motivated and detail-oriented Design Verification Engineer to join our growing Verification team. In this role, you will contribute to the verification of cutting-edge SoCs and IPs targeting AI, HPC, and Networking applications. You will work closely with experienced verification engineers and architects to develop testbenches, create test scenarios, analyze coverage, and help ensure high-quality silicon delivery.

This is an excellent opportunity for engineers who are passionate about digital design, verification methodologies, and next-generation semiconductor technologies.

What You'll DoDevelop and execute verification test plans for IPs, subsystems, and SoC components.Create and maintain SystemVerilog/UVM-based verification environments.Write directed and constrained-random test cases to validate design functionality.Develop functional coverage models and assist in coverage closure activities.Debug simulation failures and collaborate with design engineers to resolve issues.Write assertions (SVA) to improve design checking and verification quality.Participate in regression execution, result analysis, and reporting.Support IP integration and subsystem-level verification activities.Learn and apply industry-standard verification methodologies and best practices.Contribute to automation scripts for regression, reporting, and verification productivity.Work closely with Design, Architecture, and Software teams to understand requirements and verify functionality.What We're Looking ForBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.2–7 years of experience in Design Verification or Digital Design.Strong understanding of digital design fundamentals and computer architecture.Knowledge of:Verilog/SystemVerilogUVM methodologySimulation and debugging conceptsFunctional and code coverageBasic scripting (Python, Perl, Shell, or TCL)Familiarity with verification tools from Synopsys, Cadence, or Siemens EDA.Understanding of common bus protocols such as AXI, APB, AHB, PCIe, or Ethernet is a plus.Good analytical and debugging skills.Strong communication and teamwork abilities.Preferred QualificationsInternship or academic project experience in ASIC/SoC verification.Exposure to SystemVerilog assertions (SVA).Knowledge of constrained-random verification techniques.Experience with Python-based automation.Understanding of AI, HPC, or Networking architectures is a plus.Familiarity with Git or other version-control systems.Key AttributesStrong learning mindset and curiosity about semiconductor technologies.Attention to detail and commitment to quality.Problem-solving attitude with a willingness to learn from challenges.Ability to work effectively in a collaborative environment.Passion for innovation, automation, and continuous improvement.