Senior Manager, Physical Design in SAINT PAUL, Minnesota at ForwardEdge ASIC LLC

At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design.

As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents.

We are seeking an experienced Senior Manager of IC Physical Design to lead and grow our Physical Design organization supporting the development of advanced ASICs and mixed-signal semiconductor products.

The Senior Manager will be responsible for maintaining and building a high-performing physical design team and establishing disciplined, scalable methodologies for RTL-to-GDSII implementation, timing closure, physical verification, power optimization, and tapeout. This role will work closely with Architecture, RTL Design, DFT, Analog/Mixed-Signal, Packaging, Verification, Foundry, and Product Engineering teams to deliver high-quality silicon on schedule.

This position is ideal for a technical leader who wants to combine hands-on ASIC expertise with building the physical design capabilities required for long-term semiconductor product development.

• Lead the physical design organization responsible for complete RTL-to-GDSII implementation of advanced ASIC products.

• Maintain physical design methodologies, flows, standards, and quality requirements.

• Provide technical leadership for:

o Floorplanning and partitioning

o Power planning

o Placement and optimization

o Clock-tree synthesis

o Routing

o Static timing analysis and timing closure

o Signal integrity and noise analysis

o IR drop and electromigration analysis

o Physical verification

o Design-for-manufacturing

o ECO implementation

o Tapeout readiness

• Drive design closure against PPA — performance, power, and area — objectives.

• Establish design reviews, implementation checkpoints, and tapeout readiness criteria.

• Identify technical risks early and develop mitigation plans.

• Recruit, develop, mentor, and retain a high-performing physical design engineering team.

• Establish team structure, responsibilities, development plans, and technical ownership.

• Assign engineering resources across multiple ASIC programs based on priority and schedule.

• Establish engineering performance expectations and development objectives.

• Build a culture of accountability, technical excellence, collaboration, and predictable execution.

• Own physical design schedules, milestones, resource requirements, and execution plans.

• Work with Program Management to establish realistic tapeout schedules.

• Collaborate with all ASIC engineering groups.

• Track critical path activities and proactively address schedule risks.

• Coordinate physical design activities across multiple ASIC programs and technology nodes.

• Provide regular technical and program status updates to senior engineering leadership.

• Support implementation on advanced semiconductor technology nodes.

• Lead physical design activities associated with new process-node bring-up.

• Work with foundry partners on technology files, design rules, libraries, extraction, timing models, and signoff requirements.

• Evaluate technology-node tradeoffs affecting performance, power, area, cost, yield, and schedule.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

• 10+ years of semiconductor/ASIC physical design experience, including significant experience leading physical implementation.

• 5+ years of engineering management or technical leadership experience.

• Demonstrated experience taking ASICs from RTL through GDSII/tapeout and silicon.

• Demonstrated success managing engineers, schedules, priorities, external partners, and technical risk.

• Strong understanding of modern physical design methodologies and ASIC implementation.

• Experience working with advanced CMOS process technologies.

• Strong understanding of ASIC design flows and semiconductor manufacturing requirements.

• Demonstrated ability to lead engineers and manage multiple priorities simultaneously.

• Excellent written and verbal communication skills.

• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off

• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO

• Incentives: Eligibility for short-term and long-term incentive programs