Staff Engineer - Design Verification in India at Jobgether

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Staff Engineer - Design Verification based in India.

This is a senior technical leadership opportunity focused on verifying next-generation high-speed interconnect IP and SoC technologies. You will define verification strategy and architecture for complex protocols including PCIe, CXL, Ethernet, and UCIe. The role combines deep hands-on engineering with technical leadership, from building reusable UVM environments to driving coverage closure and silicon-level debug. You will work closely with design, architecture, and validation teams in a highly collaborative, globally distributed engineering environment. The position offers the opportunity to influence verification methodologies across sophisticated chiplet, AI, and high-performance computing architectures. You will also mentor engineers and establish verification practices that can scale across multiple projects and tape-outs. This is an ideal role for an experienced verification expert who wants meaningful ownership over challenging semiconductor designs.

• Define and lead scalable verification strategies and plans for complex PCIe, CXL, Ethernet, and UCIe subsystems.
• Architect and develop layered, reusable UVM agents, environments, testbenches, and verification components for high-speed protocol verification.
• Drive verification of advanced standards including PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, and UCIe PHY and Adapter layers.
• Establish coverage-driven verification strategies and lead functional coverage closure, assertion-based verification, SVA, and metric-driven sign-off.
• Lead complex debugging and root-cause analysis across simulation, emulation, prototyping, and silicon bring-up environments.
• Collaborate closely with design, architecture, and validation teams to identify risks, resolve issues, and deliver robust IP and SoC implementations.
• Develop verification frameworks and reusable methodologies that can be applied across multiple projects and tape-outs.
• Provide technical leadership and mentorship to junior and mid-level verification engineers, promoting strong engineering practices and protocol expertise.
• Contribute to improvements in verification productivity through advanced methodologies, automation, and emerging AI/ML-based verification approaches.
• Support performance, power-aware, and other advanced verification activities where required.

• 8+ years of professional Design Verification experience, with significant exposure to complex SoC and IP verification.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Proven ability to define and deploy verification architectures for complex, high-speed interfaces and protocols.
• Strong hands-on expertise in SystemVerilog, UVM, coverage-driven verification, and SystemVerilog Assertions (SVA).
• Deep practical experience with one or more high-speed protocols, particularly PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, or comparable technologies.
• Strong understanding of UCIe PHY and Adapter layer verification is highly desirable.
• Solid understanding of SoC architecture, high-speed interfaces, IP integration, and complex semiconductor verification flows.
• Strong C and SystemVerilog programming skills, with the ability to develop sophisticated verification environments and reusable components.
• Exceptional debugging, analytical, and problem-solving capabilities, including experience tracing complex issues across multiple verification stages.
• Demonstrated technical leadership and the ability to influence verification strategy and engineering decisions.
• Strong mentoring and communication skills, with the ability to collaborate effectively across global engineering teams.
• Experience with emulation, prototyping, or hybrid verification platforms is a plus.
• Familiarity with performance verification and power-aware verification methodologies is beneficial.
• Knowledge of industry-standard protocols such as PCIe, DDR, Ethernet, CXL, and UCIe is advantageous.
• Experience applying AI/ML techniques or tools to verification workflows is a plus.

• Remote-friendly opportunity for candidates based in India.
• Opportunity to work on next-generation semiconductor infrastructure for AI and high-performance computing.
• High level of technical ownership and influence over verification architecture and methodology.
• Exposure to advanced chiplet, high-speed interconnect, and custom silicon technologies.
• Opportunity to work with challenging protocols including PCIe, CXL, Ethernet, and UCIe.
• Collaboration with experienced semiconductor engineers across India and the United States.
• Fast-paced engineering environment with minimal bureaucracy and an emphasis on technical execution.
• Opportunity to build reusable verification frameworks and methodologies across multiple silicon projects and tape-outs.
• Significant scope for technical leadership, mentorship, and career growth.
• Opportunity to contribute to products addressing critical infrastructure challenges in the rapidly growing AI/HPC semiconductor ecosystem.