Staff ASIC Design Engineer in SAINT PAUL, Minnesota at ForwardEdge ASIC LLC
NewSalary: $140000 - $170000Employment Type: Full-TimeExperience Level: NoneMinimum Education: None
ForwardEdge ASIC LLC
SAINT PAUL, Minnesota, 55108, United States
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Job Description
Position Description: At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design.
As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents.
Job Summary
We are currently seeking a Staff ASIC Design Engineer responsible for developing ASIC and FPGA designs that will be included in an array of complex, innovative and exciting products. Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work closely with verification, analog design, physical design and architecture teams.
Key Responsibilities:
• Providing leadership to lower-level engineers and working with architects to understand the function and requirements for all types of digital design blocks.
• Define, document and design digital/analog interfaces.
• Writing detailed implementation plans and specifications for complex design blocks.
• Writing Register Transfer Level (RTL) code using industry standard hardware description languages.
• Writing lower-level test bench code to verify baseline functionality and features for design blocks.
• Writing test plans and coordinating with the Design Verification team to fully verify design blocks.
• Synthesizing RTL code using industry standard tools and analyzing results.
• Providing RTL updates to meet Power, Performance and Area (PPA) requirements.
• Writing and executing plans for the post silicon lab validation.
• Providing continued support for design blocks working within a larger system level environment through productization and production.
• Process and methodology automation utilizing common scripting languages (i.e. python, perl, tcl).
• Provide mentorship and guidance to lower-level digital design engineers.
Qualifications:
• Bachelor’s or master’s degree in electrical or computer engineering.
• Relevant prior experience working at this level as a Staff ASIC Design Engineer.
• Experience with RTL coding languages and industry common scripting languages.
• Technical leadership experience is a plus.
What We Offer
• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off
• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO
• Incentives: Eligibility for short-term and long-term incentive programs
Join ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world.
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Job Location
SAINT PAUL, Minnesota, 55108, United States
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