Lead SoC Architect in Sunnyvale, California at Bolt Graphics

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

Our Values

Be Fearless: Unmute yourself. Test boundaries and get proven right.Remain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role:

We are looking for an experienced and highly motivated Lead SoC Architect to lead the architecture definition and technical direction for next-generation semiconductor products. The ideal candidate will have strong expertise in complex SoC architecture development, performance modeling, subsystem integration, and cross-functional collaboration across hardware, software, and system teams.

This role involves defining scalable and high-performance architectures for advanced compute platforms including AI, GPU, multimedia, networking, RISC-V or datacenter-class SoCs. This is a tech lead role and requires on-site presence in our Sunnyvale office. The ideal candidate must be willing to be an individual contributor while leading others. This role is on-site and requires someone to be local to the Bay Area.

What you'll do:

Define top-level SoC architecture and subsystem partitioning for complex semiconductor products. Drive architecture tradeoff analysis for performance, power, area, bandwidth, latency, and scalability. Develop and review system architecture specifications, interface definitions, and microarchitecture requirements. Collaborate with RTL, verification, physical design, firmware, software, and system teams throughout the development cycle. Lead performance modeling, workload analysis, and bottleneck identification using C/C++/SystemC or similar modeling environments. Define memory hierarchy, NoC/interconnect strategy, coherency architecture, and cache structures. Evaluate and integrate third-party IPs including CPU, GPU, NPU, PCIe, DDR/LPDDR, Ethernet, multimedia, and security subsystems. Work closely with verification teams to define architectural test plans and validation strategies. Support silicon bring-up, debug, performance tuning, and post-silicon optimization. Contribute to long-term technology and product roadmap planning.

Required Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 10+ years of experience in SoC architecture, ASIC development, or complex semiconductor system design. Strong understanding of modern SoC architectures and subsystem integration. Experience with one or more of the following: CPU/GPU/NPU architectures NoC/interconnect architectures Cache coherency protocols (CHI/ACE/CXL) High-speed interfaces (PCIe, UCIe, Ethernet) Memory systems (DDR5, LPDDR5X, HBM) Power/performance optimization Strong knowledge of RTL development and verification methodologies. Experience with architecture modeling and performance analysis tools. Familiarity with firmware/software interaction in complex SoC systems. Excellent problem-solving, communication, and leadership skills.

Preferred Qualifications

Experience with AI accelerator, GPU, networking, RISC-V or datacenter SoC architectures. Experience with chiplet-based or multi-die architectures. Familiarity with advanced process technologies and package integration. Experience with emulation, FPGA prototyping, and system-level validation. Knowledge of Linux drivers, runtime software, or system software architecture. Prior technical leadership experience across cross-functional engineering teams.

Technical Skills

System architecture definition C/C++/SystemC modeling Performance analysis and simulation RTL and microarchitecture understanding AMBA/AXI/CHI protocols PCIe/CXL/UCIe Memory subsystem architecture HW/SW co-design Silicon bring-up and debugging

Compensation Range: $200,000–$250,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.

Benefits:

Medical, Dental, & Vision - 100% covered premiumsEquity - Stock Options401(k) matchWFH Hardware

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.