Senior Engineer – Physical Verification (PV) in Remote, Karnātaka at TylSemi, Inc.

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.

• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location

• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.

• Bias for action. We move fast. Analysis paralysis doesn't fly here.

• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are looking for a highly motivated Senior Engineer – Physical Verification (PV) to join our Physical Design team. In this role, you will be responsible for driving block-level and full-chip physical verification signoff for advanced-node SoC designs. You will work closely with Physical Design, Layout, and Foundry teams to ensure high-quality and timely tapeouts. The role requires strong expertise in DRC/LVS methodologies, debugging complex violations, and improving PV automation flows.

What You’ll Do

Perform block-level and full-chip Physical Verification including DRC, LVS, ERC, antenna, and density checks Drive PV closure and debug complex violations in collaboration with Physical Design and Layout teams Execute hierarchical and flat verification methodologies for advanced-node designs Develop and maintain PV runsets, automation scripts, and signoff flows Analyze foundry rule decks and ensure design compliance with process requirements Optimize verification runtime, memory usage, and turnaround time Support tapeout activities and ensure clean signoff delivery

What We’re Looking For

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline 5+ years of hands-on experience in Physical Verification or Physical Design signoff Strong understanding of DRC, LVS, ERC, antenna, and density verification concepts Hands-on experience with Mentor Calibre and exposure to Synopsys ICV is a plus Good understanding of CMOS fundamentals, layout effects, and advanced-node design rules Proficiency in Tcl, Perl, Python, or Shell scripting for automation and flow development

Good to Have

Experience with advanced technology nodes such as 7nm, 5nm, or below Exposure to FinFET technologies and multi-patterning design rules Knowledge of reliability checks such as ESD, latch-up, and parasitic extraction/debug

Success in This Role Looks Like

Achieving clean PV signoff with minimal iterations and timely tapeout support Efficient debugging and closure of complex DRC/LVS violations Improved verification productivity through automation and methodology enhancements Strong collaboration across cross-functional teams leading to successful project execution