Principal SI/PI, Package and Power Delivery Engineer in Bangalore, Karnātaka at TylSemi, Inc.

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.

• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location

• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.

• Bias for action. We move fast. Analysis paralysis doesn't fly here.

• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

As an SI/PI, Package and Power Delivery Engineer at Tylsemi, you will own signal integrity, power integrity, and package/PDN co-design across chip, package, and board interfaces. You will work closely with SoC, physical design, analog, package, board, and validation teams to ensure robust high-speed links, stable power delivery, and predictable signoff from early architecture through tapeout and bring-up. This role is ideal for engineers who enjoy cross-domain problem solving and turning complex electrical constraints into clean, manufacturable solutions.

What You’ll Do

Drive SI/PI methodology and execution from early planning through signoff for high-speed interfaces and power delivery networks Perform package/board/chip co-design: define stackups, routing constraints, via strategies, reference planes, and return-path integrity Model and analyze high-speed channels (e.g., SerDes, DDR, PCIe, USB, Ethernet) including insertion/return loss, crosstalk, jitter, eye margins, and equalization tradeoffs Build and validate electrical models (IBIS/IBIS-AMI, S-parameters, SPICE) and ensure model correlation and version control hygiene Own PDN design and analysis across die/package/board: impedance targets, decap strategy, anti-resonance mitigation, and rail stability Run PI signoff including DC/AC IR drop, EM, dynamic droop/noise, and power/ground bounce; drive fixes with clear, reviewable action plans Partner with physical design and signoff teams on power grid architecture, bump/ball planning, current density limits, and rail partitioning Collaborate with package engineering on substrate routing, escape, ballout, and manufacturability constraints; review and approve package design deliverables Define and enforce design rules/constraints for routing, spacing, shielding, length matching, and reference plane transitions Support lab bring-up and correlation: translate silicon/package/board measurements into model updates and design improvements Create and maintain automation, checks, and reporting (Python/Tcl or equivalent) to improve predictability, repeatability, and execution speed Contribute to tapeout readiness: documentation, checklists, design reviews, and root-cause analysis to prevent recurrence

What We’re Looking For

Hands-on experience delivering SI/PI and package/PDN solutions for complex SoCs (scope aligned to level of experience) Strong fundamentals in transmission lines, S-parameters, impedance, return paths, coupling/crosstalk, and power delivery behavior across frequency Ability to translate system requirements into actionable constraints and to drive closure across multiple teams and design stages Methodical debug skills: clear problem statements, data-driven root cause, and practical mitigation plans Strong communication and engineering hygiene: reproducible analyses, clean documentation, and review-friendly deliverables

Required Skills

Signal Integrity (SI) analysis for high-speed interfaces Power Integrity (PI) / PDN design and analysis (chip-package-board) Package and power delivery co-design (substrate/ballout/bumps, stackup and routing constraints) Electrical modeling (S-parameters, SPICE, IBIS/IBIS-AMI) and correlation mindset Cross-functional execution with SoC/PD/analog/package/board/validation teams

Nice to Have

Experience with industry tools for SI/PI and package analysis (e.g., HFSS, SIwave, ADS, HSPICE/Spectre, PowerSI, Clarity, Ansys RedHawk/Voltus or equivalents) DDR/LPDDR and SerDes compliance experience (channel budgets, jitter/noise decomposition, margining) Advanced packaging exposure (2.5D/3D, interposers, chiplets, HBM, CoWoS/EMIB-like concepts) and related SI/PI challenges Thermal-awareness in PDN/package decisions and collaboration with thermal/mechanical teams Experience defining signoff criteria, templates, and reusable flows across programs

Success in This Role Looks Like

Predictable SI/PI closure with clear milestones, risk tracking, and minimal late-stage surprises Robust package/PDN solutions that meet impedance/noise/jitter targets and scale cleanly to production Fast, high-quality debug and mitigation of SI/PI issues with strong cross-team alignment Well-documented, reproducible analyses and signoff artifacts that improve team velocity and tapeout readiness