CNO Instructor II - Computer Organization and Architecture at COMTECH TELECOMMUNICATIONS – Pensacola, Florida

Title: CNO Instructor (Computer Organization and Architecture)

Department: Cyber Services/Div 12

Revision date: 1/12/2026

FLSA Status: Exempt

Location: Pensacola, FL

Level: T2

Company Overview

Comtech Telecommunications Corp. is a leading global technology company providing terrestrial and wireless network solutions, next-generation 9-1-1 emergency services, satellite and space communications technologies, and cloud-native capabilities to commercial and government customers around the world. Our unique culture of innovation and employee empowerment unleashes a relentless passion for customer success. With multiple facilities located in technology corridors throughout the United States and around the world, Comtech leverages our global presence, technology leadership, and decades of experience to create the world’s most innovative communications solutions. For more information, please visit www.comtech.com.

We’re seeking curious, growth-minded thinkers to help shape our vision, structures, and systems; playing a key role as we launch into our ambitious future. If you’re invigorated by our mission, values, and drive to change the world — we’d love to have you apply.

Responsibilities:

Comtech Systems, Inc. (CSI) is looking for professional instructors to deliver Cyberspace Operations (CO) training to Department of Defense personnel at the Center for Information Warfare Training (CIWT), Corry Station, Pensacola, FL.

• Perform duties as CO Instructor for Computer Organization & Architecture by delivering highly technical training in a military training environment consisting of lectures, labs, exercises and other delivery methods.
• Assist with developing CO training curriculum (lecture content, student/instructor guides, exams, exercises, simulations, etc.).

Requirements:

• All candidates must possess strong oral and written communication skills. Candidates shall provide classroom instruction that teaches assigned students in the manner described in the course Program of Instruction. Candidates shall conduct practical exercises in a laboratory environment, conduct student study hall periods, and provide tutoring/remedial instruction for up to twenty students per class.
• All candidates must possess the ability to incorporate/impart technical knowledge into their training delivery.
• Assess student knowledge, skills, and abilities to gauge student proficiency in topic areas.
• Deliver instruction via interactive synchronous and asynchronous learning activities.
• Review and analyze training materials and recommend changes.
• Applicants must possess the ability to obtain and maintain a security clearance at the level required by each assigned task.

Qualifications:

• Experience in adult learning with an emphasis on providing instruction to large classes. US Military instructor certification or designation is highly desirable (e.g., teaching certificate, certified professional instructor, master training specialist, adjunct faculty certification).
• Applicant should have intermediate-level knowledge/experience in the following areas, unless otherwise indicated:
  • Digital Logic and Digital Systems:
  • Overview and history of computer architecture
  • Combinational vs. sequential logic/Field programmable gate arrays as a fundamental combinational + sequential logic building block
  • Multiple representations/layers of interpretation (i.e. hardware is just another layer)
  • Computer-aided design tools that process hardware and architectural representations
  • Register transfer notation/Hardware Description Language (e.g. Verilog/VHDL)
  • Physical constraints (e.g. gate delays, fan-in, fan-out, energy/power)
• Machine-level Representation of
  • Bits, bytes, and words
  • Numeric data representation and number bases
  • Fixed- and floating-point systems
  • Signed and twos-complement representations
  • Representation of non-numeric data (e.g. character codes, graphical data)
  • Representation of records and arrays
• Assembly Level Machine Organization:
  • Basic organization of the von Neumann machine
  • Control unit; instruction fetch, decode, and execution
  • Instruction sets and types (e.g. data manipulation, control, I/O)
  • Assembly/machine language programming
  • Instruction formats
  • Addressing modes
  • Subroutine call and return mechanisms
  • I/O and interrupts
  • Heap vs. Static vs. Stack vs. Code segments
  • Shared memory multiprocessors/multicore organization
  • Introduction to SIMD vs. MIMD and the Flynn Taxonomy
• Memory System Organization and Architecture:
  • Storage systems and their technology
  • Memory hierarchy: importance of temporal and spatial locality
  • Main memory organization and operations
  • Latency, cycle time, bandwidth, and interleaving
  • Cache memories (i.e. address mapping, block size, replacement and store policy)
  • Multiprocessor cache consistency/Using the memory system for inter-core synchronization/atomic memory operations
  • Virtual memory (i.e. page table, TLB)
  • Fault handling and reliability
  • Error coding, data compression, and data integrity
• Interfacing and Communication:
  • I/O fundamentals: handshaking, buffering, programmed I/O, interrupt-driven I/O
  • Interrupt structures: vectored and prioritized, interrupt acknowledgment
  • External storage, physical organization, and drives
  • Buses: bus protocols, arbitration, direct-memory access (DMA)
  • Introduction to networks: communications networks as another layer of remote access
  • Multimedia support
  • RAID architectures
• Functional Organization
  • Implementation of simple datapaths, including instruction pipelining, hazard detection and resolution
  • Control unit: hardwired realization vs. microprogrammed realization
  • Instruction pipelining
  • Introduction to instruction-level parallelism (ILP)
• Multiprocessing and Alternative Architectures
  • Power Law
  • Example SIMD and MIMD instruction sets and architectures
  • Interconnection networks (e.g. hypercube, shuffle-exchange, mesh, crossbar)
  • Shared multiprocessor memory systems and memory consistency
  • Multiprocessor cache coherence
• Performance Enhancements
  • Superscalar architecture
  • Branch prediction, Speculative execution, Out-of-order execution
  • Prefetching
  • Vector processors and GPUs
  • Hardware support for multithreading
  • Scalability
  • Alternative architectures, such as VLIW/EPIC, and Accelerators and other kinds of Special-Purpose Processors

Education:

• Bachelor’s Degree plus two (2) years of experience in Cyberspace Operations (CO). Experience in CO is defined as experience in Defensive Cyberspace Operations (DCO), and/or Offensive Cyberspace Operations (OCO).
• In lieu of a degree, four (4) years of experience in Cyberspace Operations (CO).

• Additional experience, educational, or certification recommendations beyond those listed above:

1. Certifications in CompTIA Security+, GIAC Security Essentials (GSEC), or ISC2 Systems Security Certified Practitioner (SSCP) is desired

The pay range reflects the expected base salary for this position. Final compensation will be based on role, level, skills, experience, and geographic location.

Comtech Telecommunications Corp. is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability protected veteran status or other characteristics protected by law.