Senior Design Verification Engineer in India at Jobgether
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Job Description
This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Design Verification Engineer based in India.
This role sits at the core of advanced silicon development, focusing on verification of interconnect and chassis IP blocks that power next-generation computing systems. You will own end-to-end verification activities, from planning and test strategy to coverage closure and debug resolution, ensuring the highest levels of quality and reliability. The environment is highly technical, fast-paced, and collaborative, requiring close interaction with architecture, design, and software teams. You will build scalable, reusable verification frameworks and contribute directly to improving automation and efficiency across verification workflows. The role demands strong hands-on expertise in SystemVerilog/UVM and deep protocol understanding, along with the ability to independently drive complex verification tasks. You will also play an increasing role in mentoring junior engineers and shaping best practices. AI-assisted engineering tools are integrated into daily workflows, supporting productivity and innovation.
Lead end-to-end verification of IP and subsystem-level designs, ensuring robust coverage, high-quality execution, and timely delivery of verification milestones.
- Own verification planning, test development, and coverage closure for assigned IP blocks and features
- Build and maintain scalable verification environments using UVM, SystemVerilog, and constrained-random methodologies
- Develop reusable testbenches, checkers, and automation frameworks to improve verification efficiency
- Collaborate with architecture, design, and software teams for spec reviews, debugging, and issue resolution
- Drive root-cause analysis of simulation failures and ensure timely defect closure
- Execute functional coverage planning and contribute to sign-off quality metrics
- Participate in simulation and formal verification activities to enhance verification depth and confidence
- Mentor junior engineers and support continuous improvement in verification practices and code quality
You bring strong experience in design verification with a proven track record of delivering high-quality IP and subsystem verification in complex silicon environments. You are highly skilled in debugging, protocol analysis, and building reusable verification infrastructures.
- 8–12 years of experience in design verification with IP and subsystem-level exposure
- Strong expertise in interconnect protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe
- Deep knowledge of UVM, SystemVerilog, SVA, and coverage-driven verification methodologies
- Hands-on programming experience in SystemVerilog, C/C++, and Python for verification and automation
- Strong understanding of cache coherency and memory consistency models
- Experience collaborating across architecture, design, and software teams in complex projects
- Familiarity with AI-assisted development workflows for coding, debugging, and test generation
- Experience with formal verification, emulation, or FPGA-based validation is a plus
- Exposure to system-level IPs such as MMUs, interrupt controllers, or power/debug features is preferred
- Competitive compensation aligned with experience and industry standards
- Fully remote work model within India (occasional site visits as required)
- Opportunity to work on cutting-edge silicon and next-generation interconnect technologies
- Exposure to advanced verification methodologies, tools, and AI-assisted engineering workflows
- Collaborative, high-performance engineering culture with global teams
- Learning and development opportunities in advanced DV, architecture, and system design domains
- Inclusive and ethical work environment focused on innovation and engineering excellence.