Lead RTL Engineer (CPU & Processor Design) in Mexico at Jobgether

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Lead RTL Engineer (CPU & Processor Design) based in Mexico.

This is a high-impact technical leadership role within a cutting-edge semiconductor environment focused on next-generation CPU and processor innovation. The engineer will drive RTL design from microarchitecture through silicon tapeout, playing a critical role in shaping advanced compute architectures. The position blends deep hands-on RTL engineering with leadership responsibilities across cross-functional hardware teams, including architecture, verification, and physical design. You will contribute directly to performance-critical datapath and processor subsystems while ensuring robust synthesis, timing closure, and design quality. Operating in a fast-paced hardware development lifecycle, you will help translate complex architectural concepts into silicon-ready implementations. This role is ideal for an expert RTL engineer who thrives in ownership-heavy environments and enjoys solving highly complex processor design challenges.

Lead and execute end-to-end RTL design activities for CPU and processor subsystems, ensuring alignment from architectural specifications through tapeout readiness. Responsibilities include:

• Designing, developing, and optimizing RTL in SystemVerilog for processor, DSP, and datapath-intensive architectures
• Driving microarchitecture implementation, synthesis, timing closure, and performance optimization across silicon blocks
• Collaborating closely with architecture, verification, and physical design teams to ensure seamless design integration
• Owning RTL delivery milestones through GDSII handoff and supporting successful silicon tapeout execution
• Providing technical leadership, guiding design decisions, and mentoring engineering contributors on best practices
• Ensuring design correctness, scalability, and compliance with advanced semiconductor process requirements

The ideal candidate brings strong RTL engineering expertise combined with hands-on processor design experience and technical leadership capability.

• 7+ years of RTL design experience using SystemVerilog in complex hardware environments
• Proven track record leading RTL development for CPU, DSP, or processor-class silicon projects
• At least one successful silicon tapeout experience, including GDSII handoff ownership
• Strong understanding of microarchitecture, datapath design, and computer architecture principles
• Experience with synthesis, timing closure, and EDA tool-based hardware validation workflows
• Exposure to advanced process nodes (28nm or below preferred)
• Ability to lead technical discussions while remaining deeply hands-on in RTL implementation
• Strong communication, problem-solving, and cross-functional collaboration skills

• Competitive compensation aligned with industry benchmarks and experience level
• Opportunity to work on cutting-edge CPU and semiconductor architecture programs
• High-impact ownership role with direct influence on silicon tapeout success
• Flexible/remote working arrangements depending on location and project needs
• Exposure to advanced processor design and next-generation compute technologies
• Collaborative, engineering-driven environment focused on technical excellence
• Opportunity to work alongside senior architects and industry experts